VLSI Semiconductor Science & Technology · 2y ·
Latch-Up is a phenomenon where a low impedance path is created between a supply pin and ground due to unwanted noise.
Latch-up Prevention Techniques
- Keep supply voltage below the maximum voltage.
- Keep NMOS & PMOS as far as possible.
- Use oxide trenches and buried oxide layers to isolate NMOS and PMOS devices.
Fore more detail about latch-up click here
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