This is perhaps the most easily confusing term of semiconductors. We can see many explanations on the internet, such as the gate length, the optical resolution, or the smallest feature size. However, the reality is much more complex than that. I’ll try to give an explanation as simple as possible.

In the good old days the nanometer number was rather well defined. It means the smallest feature on the chips, which is virtually always the length of the gate electrode (aka the distance between the source and the drain). In another word, the three parameters I listed above were all correct as they meant the same thing.

However, as transistors are becoming smaller and smaller, those parameters began to decouple from each other. The turning point occurred when the gate length became smaller than the wavelength of the light source of photolithography. This is quite important because when the resolution is lower than the wavelength, you can still polish your lenses to achieve a better resolution. However, the resolution won’t improve indefinitely because even lights emitted from a perfect point source and focused by a perfect lens would still converge into a disk (Airy disk) roughly of the size of the wavelength. The diameter of the Airy disk sets the limit of the resolution of photolithography. That’s why over the past 30 years the semiconductor industry has shifted from mercury lamps (365 nm) to KrF excimer (248 nm), ArF excimer (193 nm), and eventually extreme ultraviolet (13.5 nm). However, switching to a different wavelength is very challenging because you basically need to redesign your light sources, photoresists and even the lenses (for example, EUV uses mirrors instead of lenses). That’s why while the wavelength is also shrinking, it can never keep up with the Moore’s law. For example, while the latest chips are claimed to be of 3nm, they are made by EUV machines of an actual resolution of 13nm. In another word, the nanometer number no longer means the optical resolution of lithography.

So how can Moore’s law continue despite the slow progress of lithography? There are several ways to work around that. The first is increasing the numerical aperture by immersion, which is not hard to understand because the wavelength of lights is greatly reduced under water. Such immersion lithography worked miraculously well on 193nm. Unfortunately, EUV is not suitable for immersion because EUV is strongly absorbed by whatever materials. The second trick is multiple patterning. For example, you can first make some walls using lithography. Then you grow a thin cover layer and remove the walls, leaving the thin sidewalls behind. This technique is capable of making extremely small features even smaller than the nominal nanometer numbers. For example, the Intel 22nm chips used FinFET of only 8 nanometers thick. In another word, if you use the fin width to represent the chip, even 22nm is an understatement. Another way is packing transistors as densely as possible at the cost of greatly increased complexity of interconnect. In the good old days a CPU needs only 6 layers of metal wires. Nowadays nearly 20 layers of wires are needed. I can swear that if each transistor is a house and each wire is a street, it would be more complex than the map of the USA!

So you can see that the nanometer number nowadays has little to do with the fabrication process. Instead, it’s calculated by comparing the transistor number with older chips. This may cause some ambiguity because chips can have different transistor densities (depending on micro architectures) and transistor sizes (depending on the foundries) even if their gate lengths are the same, which is why the it receives criticism. Nevertheless, the nanometer number is still a useful marker for chip performance.