SystemVerilog was started to merge a number of disjoint verification languages such as Vera and e that were built as a layer on top of Verilog and VHDL. Each of these languages had their own proprietary methodologies (RVM and eRM) that provided a re-useable framework to construct, configure, and execute tests.

Once SystemVerilog became established, it needed its own methodology and Mentor created the AVM(Advanced Verification Methodology) in 2006 that was derived from concepts in SystemC. Synopsys converted their Vera-based RVM(Reuse Verification Methodology) library to SystemVerilog and called it VMM(Verification Methodology Manual), but did not make it publicly available. Mentor and Cadence joined together and created the OVM (Open Verification Methodology) in 2008, which was the merging of the existing AVM with concepts from eRM.

Finally by 2011, Mentor, Cadence, and Synopsys joined together through Accellera and created the UVM(Universal Verification Methodology). The Register Abstraction Layer was derived from VMM.

One can argue all day about the differences and who did what first between the different methodologies, but they all serve the same purpose - to provide a standard methodology based on common design patterns in software programming. Take one of the most simple concepts -reporting. These methodologies give you a standard of fatal, error, warning, and info reports and a way to filter those messages. Anyone looking at the code will be able to understand how reports are generated and controlled, and it will be the same from project to project.