VMM, OVM and UVM are all different verification methodologies that evolved over last 10+ years as different verification languages and methodologies were evolving.
The main focus of all of these methodologies was to define a modular and re-usable architecture for testbench and stimulus and also comes with a standard base class library to facilitate development.
Following diagram shows in terms of history how these different methodologies evolved. VMM was proprietary to Synopsys while AVM was proprietory to Mentor Graphics.
(Ref: Verifying SoCs from the Inside Out)
OVM was an effort from Cadence and Mentor to make their methodologies open source and sooner Synopsys also also joined to make a new Universal Verification methodology.
There are differences in these methodologies based on how they evolved and how some of them was supporting backward compatibility.
OVM and UVM (Universal Verification Methodology) are SystemVerilog language based Verification methodologies and UVM is getting more and more popularity and adoption in the VLSI Verification industry. The methodology is currently in the IEEE working group 1800.2 and is expected to be an IEEE standard shortly.
If you want to know exactly what the methodology is , it is a topic of itself to learn
You might want to read following answers