This might have been true 10 years back but not any more. Traditionally Verification engineers were considered as those who run some directed tests on a design and check for functional correctness and nothing more.

Design complexities has increased tremendously in last 10 years and continues to grow exponentially such that Verifying a design has become more complex than design. Also the the number of verification engineers per design also is increasing and I have personally seen same in last several years.

I found following two graphs from a key note by Harry Foster, Chief Scientist at Mentor Graphics very interesting and are based on actual research conducted in semiconductor industry. (Reference: Industry Data and Surveys ) The first graph shows that for about 20% of design projects in the industry, an average of 70% of project time is spend for Verification. The second graph shows the need for increasing number of Verification engineers compared to design engineers over several years.

One of the important underlying concept for this trend is the increase in scope of Verification engineers from mere functional verification to a broad spectrum of other areas like Power, clocks, Security, Hardware/Software Co-verification, Formal verification, Performance Verification etc which are increasingly crucial for any design to be successful.

These new areas provides more opportunities for Verification engineers in terms of career and enhancing skills. There is continuous innovations in each of these Verification domains as every company looks for better and efficient ways to improve efficiency and productivity in Verification. This is the only way an increasingly complex design can be successfully taped out in a market driven schedule.

Functional Verification now demands more software skills like object oriented programming in addition to better understanding of hardware and logic design. Equally important is the analytical thinking ability of Verification engineers to identify and verify all design features/scenarios efficiently in shorter time. SystemVerilog language and UVM (Universal Verification Methodology) has also gained wider acceptance in industry to support this and mastering these are very challenging.

Power aware Verification and Clock domain Crossing Verification are also now considered important and critical to Verification as designs have increasing number of asynchronous clock domains and multiple power domains. Meeting the power intent of design is considered crucial for any design wins as market demands products with lower power and better performance.

Formal Verification and Assertion based Verification is another area that is seeing more adoption to designs for comprehensive verification of certain areas. Improved tools and standard formal verification apps are becoming popular and gives more scope and challenges to Verification engineers.

Designs are also trending to become more of System on Chip (SOC) and hence there is a need of System level verification and Hardware+Software Co-Verification to make sure that not just the hardware but the entire system works. Hence there is increasing of scope for FPGA/emulation based prototyping and the need of Software and hardware verification engineers to work closely. This is another area with its own challenges for Verification engineers.

So in summary I dont think you can consider a design/architecture job is better than Verification. Of course every engineer will have his own areas of interest, but based on above trends, a career in Verification is equally interesting and challenging.

There is equal involvement of Verification engineers in product definition/architecture phase, design phase, Software development and even customer interactions and I have personally seen some great people in Verification who are respected more in the company along with the design/architects/Software engineers.

Hope this helps and would like to hear comments/questions if any .

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